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SI9120
Vishay Siliconix
Off-Line Power SI9120
Universal Input Switchmode Controller
FEATURES
* 10- to 450-V Input Range * Current-Mode Control * 125-mA Output Drive * Internal Start-Up Circuit * Internal Oscillator (1 MHz) * SHUTDOWN and RESET
DESCRIPTION
The SI9120 is a BiC/DMOS integrated circuit designed for use in low-power, high-efficiency off-line power supplies. High-voltage DMOS inputs allow the controller to work over a wide range of input voltages (10- to 450-VDC). Current-mode PWM control circuitry is implemented in CMOS to reduce quiescent current to less than 1.5 mA. A CMOS output driver provides high-speed switching for MOSFET devices with gate charge, Qg, up to 25 nC, enough to supply 30 W of output power at 100 kHz. These devices, when combined with an output MOSFET and transformer, can be used to implement single-ended power converter topologies (i.e., flyback and forward). The SI9120 is available in a 16-pin plastic DIP and SOIC packages, and is specified over the industrial, D suffix (-40 to 85C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
Applications information may also be obtained via FaxBack, request document #70580 and #70578.
FaxBack 408-970-5600, request 70006 www.siliconix.com
S-60752--Rev. F, 05-Apr-99 1
SI9120
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to -VIN (Note: VCC < +VIN + 0.3 V) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 V Logic Inputs (RESET SHUTDOWN, OSC IN, OSC OUT). . . . . . . . . . . -0.3 V to VCC + 0.3 V Linear Input (FEEDBACK, SENSE, BIAS, VREF) . . . . . . . . . . . . . . . . .-0.3 V to 7 V HV Pre-Regulator Input Current (continuous). . . . . . . . . . . . . . .5 mAa Continuous Output Current (Source or Sink) . . . . . . . . . . . . . 125 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Operating Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 85C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Power Dissipation (Package)b 16-Pin Plastic DIP (J Suffix)c . . . . . . . . . . . . . . . . . . . . . . . . . 750 mW 16-Pin SOIC (Y Suffix)d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (JA) 16-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167C/W 16-Pin SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140C/W Notes a. Continuous current may be limited by the applications maximum input voltage and the package power dissipation. b. Device mounted with all leads soldered or welded to PC board. c. Derate 6 mW/C above 25C. d. Derate 7.2 mW/C above 25C.
RECOMMENDED OPERATING RANGE
Voltages Referenced to -VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9.5 V to 13.5 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 V to 450 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 k to 1 M Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC - 3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC
SPECIFICATIONSa
Test Conditions Unless Specified Parameter Reference
Output Voltage Output Impedancee Short Circuit Current Temperature Stabilitye VR ZOUT ISREF TREF VREF = -VIN OSC IN = - VIN (OSC Disabled) RL = 10 M Room Full Room Room Full 3.88 3.82 15 70 4.0 30 100 0.5 4.12 4.14 45 130 1.0 V k A mV/C
Limits
D Suffix -40 to 85C
Symbol
DISCHARGE = -VIN = 0 V, VCC = 10 V +VIN = 300 V RBIAS = 390 k, ROSC = 330 k
Tempb
Minc
Typd
Maxc
Unit
Oscillator
Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficient
e
fMAX fOSC f/f TOSC
ROSC = 0 CSTRAY Pin 9 5 pF, ROSC = 330 k CSTRAY Pin 9 5 pF, ROSC = 150 k f/f = f(13.5 V) - f(9.5 V) / f(9.5 V)
Room Room Room Room Full
1 80 160
3 100 200 10 200 120 240 15 500
MHz kHz % ppm/C
Error Amplifier
Feedback Input Voltage Input BIAS Current Input OFFSET Voltage Open Loop Voltage Gaine Unity Gain Bandwidthe Dynamic Output Impedancee Output Current Power Supply Rejection VFB IFB VOS AVOL BW ZOUT IOUT PSRR FB Tied to COMP OSC IN = - VIN (OSC Disabled) OSC IN = - VIN, VFB = 4 V OSC IN = - VIN OSC IN = - VIN OSC IN = - VIN Error Amp configured for 60 dB gain Source VFB = 3.4 V Sink VFB = 4.5 V 9.5 V VCC 13.5 V Room Room Room Room Room Room Room Room Room 0.12 50 60 1.0 3.92 25 15 80 1.5 1000 -2.0 0.15 70 2000 -1.4 4.08 500 40 V nA mV dB MHz mA dB
S-60752--Rev. F, 05-Apr-99 2
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SI9120
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Specified Parameter Current Limit
Threshold Voltage Delay to Outpute VSOURCE td VFB = 0 V VSENSE = 1.5 V, See Figure 1. IIN = 10 A VCC 9.4 V IPRE-REGULATOR = 10 A Room Room 1.0 1.2 100 1.4 150 V ns
Limits
D Suffix -40 to 85C
Symbol
DISCHARGE = -VIN = 0 V, VCC = 10 V +VIN = 300 V RBIAS = 390 k, ROSC = 330 k
Tempb
Minc
Typd
Maxc
Unit
Pre-regulator/Start-up
Input Voltagef Input Leakage Current VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG -VUVLO +VIN +IIN VREG VUVLO VDELTA Room Room Room Room Room 7.8 7.0 0.3 8.6 8.1 0.6 450 10 9.4 8.9 V V A
Supply
Supply Current Bias Current ICC IBIAS CL = 500 pF at Pin 5 Room Room 10 0.85 15 1.5 20 mA A
Logic
SHUTDOWN Delaye SHUTDOWN Pulse Widthe RESET Pulse Widthe Latching Pulse Width SHUTDOWN and RESET Lowe Input Low Voltage Input High Voltage Input Current Input Voltage High Input Current Input Voltage Low tSD tSW tRW tLW VIL VIH IIH IIL VIN = 10 V VIN = 0 V See Figure 3. Room Room Room Room Room -35 8.0 1 -25 5 A 25 2.0 CL = 500 pF, VSENSE = -VIN See Figure 2. Room Room Room 50 50 ns 50 100
V
Output
Output High Voltage Output Low Voltage Output Resistance Rise Timee Fall Time Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25C, Cold and Hot = as determined by the operating temperature suffix. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. e. Guaranteed by design, not subject to production test. f. 250V +VIN 380V place a 10 k, 1/4 W resistor in series with +VIN (Pin 1). 380V +VIN 450V place a 15 k, 1/4 W resistor in series with +VIN (Pin 1). Connect a 0.01 d capacitor between +VIN (Pin 1) and -VIN (Pin 6). FaxBack 408-970-5600, request 70006 www.siliconix.com S-60752--Rev. F, 05-Apr-99 3
e
VOH VOL ROUT tr tf
IOUT = -10 mA IOUT = 10 mA IOUT = 10 mA, Source or Sink CL = 500 pF
Room Full Room Full Room Full Room Room
9.7 9.5 0.3 0.5 20 25 40 40 75 30 50 75
V
ns
SI9120
Vishay Siliconix
TIMING WAVEFORMS
FIGURE 1.
FIGURE 2.
FIGURE 3.
TYPICAL CHARACTERISTICS
FIGURE 4.
S-60752--Rev. F, 05-Apr-99 4
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SI9120
Vishay Siliconix
PIN CONFIGURATIONS
Top View Order Number: SI9120DJ
Top View Order Number: SI9120DY Note: Pins 2 and 3 are removed
DETAILED DESCRIPTION
Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the SI9120 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, +VIN (pin 1) will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET which is connected between +VIN and VCC (pin 7). This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 8.6 V. If VCC is not forced to exceed the 8.6-V threshold, then VCC will be regulated to a nominal value of 8.6 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output driver disabled until VCC exceeds the undervoltage lockout threshold (typically 8.1 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will be at least 300 mV less than the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. Note: When driving large MOSFETs at high frequency without a bootstrap VCC supply, power dissipation in the pre-regulator may exceed the power rating of the IC package. For operation of +VIN > 250V a 10 k, 1/4 W resistor should be placed in series with +VIN (Pin 1). For +VIN > 380V a 15 k, 1/4 W resistor is recommended. BIAS To properly set the bias for the SI9120, a 390-k resistor should be tied from BIAS (pin 16) to -VIN (pin 6). This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 A. Reference Section The reference section of the SI9120 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the SI9120 brings the output of the error amplifier (which is configured for unity gain during trimming) to within 2% of 4 V. This compensates for input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" compensation. A MOS differential input stage provides for high input impedance. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground.
FaxBack 408-970-5600, request 70006 www.siliconix.com
S-60752--Rev. F, 05-Apr-99 5
SI9120
Vishay Siliconix
Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Typical Characteristics for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to -VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to 50% by locking the switching frequency to one half of the oscillator frequency. SHUTDOWN and RESET SHUTDOWN (pin 12) and RESET (pin 13) are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET. SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. See Table 1. Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an Output Driver The push-pull driver output has a typical on-resistance of 20- maximum switching times are specified at 75 ns for a 500-pF load. This is sufficient to directly drive MOSFETs such as the IRF820, BUZ78 or BUZ80. Larger devices can be driven, but switching times will be longer, resulting in higher switching losses. For applications information refer to AN707 (FaxBack #70580) and AN708 (FaxBack #70581). open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. TABLE 1. Truth Table for SHUTDOWN and RESET Pins SHUTDOWN
H H L L H L L
RESET
H
Output
Normal Operation Normal Operation (No Change) Off (Not Latched) Off (Latched) Off (Latched, No Change)
S-60752--Rev. F, 05-Apr-99 6
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